#ifndef __BSP_SRAM_H
#define __BSP_SRAM_H

#include "stm32f1xx.h"

/* Macro Definitions */
// Using NOR/SRAM Bank1.sector3, address bits HADDR[27,26]=10
// For IS61LV25616/IS62WV25616, address line range is A0~A17
// For IS61LV51216/IS62WV51216, address line range is A0~A18
#define Bank1_SRAM3_ADDR    ((uint32_t)(0x68000000))			
#define IS62WV51216_SIZE     0x100000   // 512*16/2bits = 0x100000, 1M bytes
#define PrestoredTest        0

/* Function Declarations */
void FSMC_SRAM_WriteBuffer(uint8_t *pBuffer, uint32_t WriteAddr, uint32_t n);
void FSMC_SRAM_ReadBuffer(uint8_t *pBuffer, uint32_t ReadAddr, uint32_t n);

int rw_8bit_test(void);
int rw_16bit_test(void);
void rw_nByte_test(void);

#if PrestoredTest == 1
void SRAM_Test(void);
#endif
#endif
